1. Field of the Invention
The present invention relates to a memory test circuit, a semiconductor integrated circuit and a memory test method, and particularly to a memory test circuit, a semiconductor integrated circuit and a memory test method that perform a test for a memory.
2. Description of Related Art
In recent years, among components mounted in a semiconductor integrated circuit, the number of memories that store data therein has been increased. For this reason, most of an area of the semiconductor integrated circuit is occupied by the memories. With such an increase in the number of memories, there is an increasing demand of improvement of a test quality and improvement of yields against manufacturing failures of the memories due to microfabrication processes.
As a method of improving the test quality, a memory test by using BIST (Built In Self Test) (hereinafter referred to as memory BIST) is widely known. By applying an arbitrary and complicated test algorism to the memory BIST, failures of various memories can be detected.
As a method of improving yields, a structure in which a redundant storage area is previously reserved in a part of data storage areas of a memory and a storage area where a failure exists is replaced with the redundant storage area (hereinafter referred to a redundancy structure) is generally adopted. In a test for the memory having the redundancy structure, the memory BIST is generally applied to all storage areas including the redundant storage area as test targets.
In such circumstances, in the memory BIST, it is required to extend a test range such that apart of a circuit (user circuit) that performs writing/reading data between a system logic and the memory is also tested at the actual speed by making use of a feature of enabling writing/reading of data to/from a memory to be tested at an actual speed.
FIG. 1 is a block diagram showing a configuration of a relief analyzing circuit for a semiconductor device as described in Japanese Patent Publication No. JP2003-36694A as a related art memory test circuit.
A related art memory test circuit includes a relief analyzing circuit 4 and an ALPG (Algorithmic Pattern Generator, test signal generating circuit) 5. The relief analyzing circuit 4 and the ALPG 5 are memory test circuits mounted to the memory BIST and are connected to a memory array 1. The memory array 1 includes an actual array portion 2 and a redundant portion 3. The ALPG 5 generates test signals such as an address signal and an expectation value, for performing the test for the memory array 1.
The relief analyzing circuit 4 includes a comparing portion 6, an address processing portion 7, a failure storing portion 8 and a relief analyzing portion 9. The comparing portion 6 compares data read from the actual array portion 2 or the redundant portion 3 with the expectation value of the ALPG 5 and determines whether or not a failure exists in the actual array portion 2 or the redundant portion 3. The address processing portion 7 receives an address signal and a redundant portion test signal from the ALPG 5 and generates an internal address for the redundant portion 3. The failure storing portion 8 stores failure information of the memory array 1 therein according to the determination of the comparing portion 6. The failure storing portion 8 includes a failure address storing portion formed by extending an actual array size by 1 bit in both of row and column directions. Thus, even when a failure occurs in the redundant portion 3, the failure storing portion 8 can simultaneously store the failure in the redundant portion 3 together with a failure in the actual array portion 2. Accordingly, the failure storing portion 8 is configured to have a virtual memory writing area that is four times as large as the actual array portion 2. The relief analyzing portion 9 performs relief analysis based on the information stored in the failure storing portion 8.
Although a relief solution for relieving a failure circuit of the memory array 1 with a redundant circuit of the redundant portion 3 is held in the relief analyzing portion 9, in the case that the relief solution represents a failure redundant circuit of the redundant portion 3 in performing a read operation, the relief analyzing portion 9 outputs another relief solution.
Relief analyzing processing as an operations of the related art memory test circuit will be described. FIG. 2 is a schematic view showing failure portions of the memory array 1 in FIG. 1.
It is assumed that the ALPG 5 performs a memory test for the actual array portion 2 and a failure 10 occurs in a part of the actual array portion 2 as shown in FIG. 2. The failure 10 that has occurred at testing of an address (0, 0) is determined as a failure by the comparing portion 6. At this time, the ALPG 5 outputs the redundant portion test signal having its signal level (logical level) of “L (Low level)” and the address signal representing the address (0, 0) (row and column addresses are n and m bits, respectively) to the address processing portion 7. In response to the redundant portion test signal of “L”, the address processing portion 7 outputs an address (0, 0) obtained by adding 1 bit of 0 (zero) as the most significant bit of the address (0, 0) represented by the address signal (row and column addresses are n+1 and m+1 bits, respectively) to the failure storing portion 8. Failure address information representing the address (0, 0) (row and column addresses are n+1 and m+1 bits, respectively) is stored in the failure storing portion 8.
It is assumed that the ALPG 5 performs a memory test for the redundant portion 3 and a failure 11 occurs at a redundant ROW0 of the redundant portion 3 as shown in FIG. 2. At this time, the ALPG 5 outputs the redundant portion test signal having its signal level of “H (High level)” to the address processing portion 7. In response to the redundant portion test signal of “H”, the address processing portion 7 outputs address (1000 . . . , 0) obtained by adding 1 (one) as the most significant bit of the address (0, 0) represented by the address signal (row and column addresses are n+1 and m+1 bits, respectively) to the failure storing portion 8. Failure address information representing the address (1000 . . . , 0) (row and column addresses are n+1 and m+1 bits, respectively) is stored in the failure storing portion 8.
As described above, although the relief solution for relieving the failure 10 with the redundant ROW0 and the failure 11 with a redundant ROW1 is held in the relief analyzing portion 9 by the relief analyzing processing. Since the failure exists at the redundant ROW0, an optimum solution for relieving the failure 10 with the redundant ROW1 is outputted.
I have now discovered the following facts.
In the related art memory test circuit, due to the configuration, an address representing only an actual array portion of a memory array to be tested is used as an interface. Accordingly, it is impossible to test the actual array portion and a redundant portion separately. For this reason, a test quality is disadvantageously lowered.